NNW in HEP: News and Recent Additions
News and Announcements
-
Irvine
Sensors 3D Neural Network Technology uses stackable FET technology
to built extremely high density NNWs. They have recently
won a US Army contract to pursue further development
of their Silicon Brain project.
-
NeuriCam
has commercialized the Totem NNW chip, developed at Trento Univ. and offers
the chip for sell.
-
Adaptive Solutions has ceased the marketing of any
components, including the CNAPS neural network chip and cards, directly
to the public market and instead is concentrating on high end OCR processing.
However, the CNAPS is still sold through secondary vendors and OEM manufacturers
such as California Scientific.(5/98)
-
See the information on RC
Module's Neuroprocessor NM6403.(5/98)
-
Siemens has closed its SNAT (Siemens Nixdorf, Advanced Technologies) division,
which originally sold the MA-16 products.
However, the chip is now sold by a new company, MediaInterface
Dresden GmbH , in a PCI card SYNAPSE3-PC.
(5/98)
-
The D0 experiment at Fermilab recently
published in Physics Review Letters two papers in which neural network
analysis techniques played a part. See Search
for Scalar Leptoquark Pairs Decaying to Electrons and Jets in pbarp Collisions
(PRL Vol.79,Nu.22, 1-Dec-1997 paper
) and Direct
Measurement of the Top Quark Mass (PRL Vol. 79, Nu.7, 18-Aug-1997,
hep-ex/9706014).
Talk
-
IBM Essonnes Lab
has created the SIZM
inline ZISC module similar to SIM memories so that mulitple ZISC chips
can be cascaded to make large numbers of neurons available. A single SIZM
has 6 ZISC chips, each with 36 neurons.
-
The H1 second level NNW trigger was
implemented in 1996 and is now running to reject events on line at HERA.
The second level runs on ten CNAPS VME
boards. See the experiments page for
more details.
-
Accurate Automation now
has an ISA card in addition to their VME card with their Neural Network
Processor (NNP) that uses a Multiple Instruction/Multiple Data architecture.
A single processor can emulate 8k neurons and achieve 140MCPS. Up to 10
processors can be connected to achieve 1.4GCPS. The system is being used
in the LoFlyte
project supported by the US Air Force to control an unmanned hypersonic
vehicle.
-
Siemen's now provides a PCI bus coprocessor card based on their MA-16
vector-matrix
multiplier chip. See the description oF the SYNAPSE2*PC.
-
See the Java demo of tracking with the elastic
net fitting method by the NEMO
software group at Dubna, Russia. See also the use of the elastic net
method with the Traveling
Salesman Problem.
-
IBM and Nestor announce at the ICANN'95 Conference in Paris Oct. 9-15,
1995 that they will collaborate on future NNW chips. Nestor
had been pursuing legal actions against IBM because of similarities in
the IBM ZISC036 learning algorithm
and Nestor's proprietary RCE algorithm. (17/10/95)
-
Nestor now offers a PCI card
with 1-4 Ni1000 chips and also a VME card with 1-4 chips.
-
Adaptive Solutions is having great success
with its NNW systems. It is reportably having trouble meeting the demand
for its boards for OCR and other applications. See their Whats
New for the latest.(17/10/95)
-
Motorola dropped development of its own NNW chip, after quite a big effort,
in fact, and is now collaborating with Adaptive
Solutions on a next generation CNAPS chip. See their PR
announcement from 1995.
Recent Additions
-
18 Jan 2000 Added Ward Systems
Group to front page list of NNW companies.
-
11 Nov 1998 Added entries for Irvine
Sensors and NeuriCam
to the hardware page. Also, put indicators on some entries that are obsolete.
-
6 May 1998 Added info to the hardware page about RC
Module's Neuroprocessor NM6403 and MediaInterface's
PCI card SYNAPSE3-PC.
-
22 Jan 1998 Updated entry for the SAND
chip for the change in the company name from INCO to datafactory.
Above is added a note about the D0 experiment using NNWs in published analysis.
-
28 May1997 Created entries on the hardware page about the Karlsruhe/SAND
neurochip and PCI card. Added links on the hardware
page to the IBM France site that describes their new ZISC inline module
SIZM.
Also, added links to two more online papers describing the H1
NNW Level 2 trigger.
-
2 April 1997 Updated links to Nestor chip
and board information on hardware
page.
-
21 March 1997 Added description and links to the Univ.
of Paderborn Pulse Coded Neural Network Accelerator on the hardware
page.
-
4 Dec 1996 Added links to Siemens Nixdorf,
Advanced Technologies on the main page and the hardware
page plus added a sales contact. Updated the Dynamind contact info
on the software page.
-
24 Oct 1996 Added link to Synaptics
-
23 Oct 1996 Added link to Neuroscience
Web Search Tool. Added to the experiments page a new abstract from
AIHENP'96 on the implementation of the H1
Second Level trigger . Added links to the IBM
Essonnes Lab - maker of the ZISC
NNW. Updated info on Accurate-Automation
and
a new web address for Sensory Inc.
-
3 Oct 1996 Added a description of the new SYNAPSE2*PC
PCI
bus coprocessor card from Siemen's.
-
22 July 1996 Added links to Applied
Neurodynamics, Analog
VLSI & Robotics Research - Univ. Indiana , Centre
for Neural Computing Applications - Brunel Univ.,GALATEA
II - Neurocomputing Esprit Project,California
Cybernetics Corp, NEuroNet
* , ELENA
* , Neural Computer Sciences,
An
Introduction To Neural Networks - Z Solutions, NNW
FAQ, and SLAC
- High Energy Physics Software
-
11 June 1996 Added links to Bruce
Denby's new home page.
-
12 May 1996 Added links to Mathematica
on the software page and the Forex
Predictor on the main page NN list.
-
25 March 1996 Removed the AND Transputer entry in the hardware section
since it is no longer available. Added a link to the AND
Corp on the software page. Added links
to the NEMO
Software group at Dubna and their Java Demos.
-
18 March 1996 Added a link to Neuroptics
Technologies which sells the IBM ZISC
chip, ISA card and PCMCIA
card. Also, added the latter to the hardware page.
-
4 March 1996 Added links to Nestor
to the hardware page. Also, an entry for the Univ. Roma circuit labs Cellular
Neural Network chips. Added the ICANN'96 conference to the conference
page.
-
1 Feb 1996 Added entries for hardware to the Cognizer
Almanac, and an entry there for Synaptics
Inc., plus links to Adaptive
Logic Inc., Mosaic Industries,
Inc., and Telebyte.
-
29 Jan 1996 Added several entries to the reference list. Added link
to AIHEP'96
on
conference page.
-
24 Jan 1996 Added several links to Hardware sites on main page.
Added entry for IC Tech chips on
hardware page.
-
23 Jan 1996 Updated info on Oxford
Computer chips and Telebyte vendor
info on hardware page.
-
17 Jan 1996 Added link on home page to TUTNC
NeuroComputer at Tampere Univ. of Technology, Finland .
-
3 Jan 1996 Added a description and links for the Sensory
Circuits NNW speech recognition chips to the hardware pages.
-
2 Jan 1996 Added a description and links for the Sundance
SMT306 Neural Processing 'C40 TIM to the hardware page. Added links
on hardware and main pages to Accurate
Automation's WWW site. Also, added links on main page to NNW sites
at Iowa State
University.
-
27 Nov 1995 Added link to California
Scientific (BrainMaker software and accelerator cards) to software
and hardware pages. They now have a CNAPS/BrainMaker
version that uses the CNAPS/PC 128
accelerator card.
-
31 Oct 1995 Added information about the Nestor
PCI and VME cards and a new Nestor vendor in England.
-
15 Oct 1995 Added information about the CDF
Tau trigger and the H1 First level
trigger to the experiments page.
-
8 Oct 1995 Added PDP++ software
to software page.
-
3 Oct 1995 Added links to Frequently
Asked Questions (FAQ) on Neural Networks p.7 - Hardware NNW and to
the Physics Instrumentation
Group at KTH, Stockholm on the top page hardware sites list.
-
22 Sept 1995 Added to the reference pages the talks given at AIHENP'95
in
Pisa last April.
-
20 Aug 1995 Added the pRAM-256
NNW chip to hardware page.
-
9 Aug 1995 Description of NeuroSolutions
added
to software page. Also, EANN'96 added to list in conference
page.
NNW/HEP
Home Page
Authors: Clark
S. Lindsey , Bruce
Denby , & Thomas
Lindblad
Curator: Clark S. Lindsey (lindsey@particle.kth.se)